This invention relates to a semiconductor device including a plurality of chips, and in particular to a semiconductor device having DLL (Delay Locked Loop) circuits.
Japanese Patent Application Publication No. 2011-029535 (Patent Document 1) discloses a semiconductor device of a COC (Chip On Chip) structure having a plurality of stacked semiconductor chips, in which a DLL circuit is mounted on each of the semiconductor chips (see FIG. 3).
Japanese Patent Application Publication No. 2008-065884 (Patent Document 2) discloses a semiconductor device of a MCM (Multi Chip Module) structure in which a clock signal is transmitted from a DLL circuit of a first chip to a second chip (See FIG. 1). A similar configuration is described also in Japanese Patent Application Publication No. 2006-013495 (Patent Document 3) and Japanese Patent Application Publication No. 2002-015567 (Patent Document 4).